1. Field of the Invention
This invention generally relates to a detection circuit, and more particularly to a jack detection circuit.
2. Description of the Related Art
The majority of the present electronic products, e.g. personal computers or multimedia products, provide at least two jacks as the transmission interface of analog signals. When a user plugs a jack or key device into the jacks, an information unit, e.g. central processing unit, recognizes the device or its signal in accordance with a jack or key state of the device or the signal outputted therefrom. A keyboard module is widely used as a jack (or key) device. When a user presses any keys on the keyboard module, it will send out an analog signal such that an information unit can recognize the keys which are pressed. Conventionally, the analog signal is utilized to control switching states of a switching circuit 90, as shown in FIG. 1, so as to change an equivalent resistance of the switching circuit 90 and further to generate a voltage signal Vin1. Afterward, the voltage signal Vin1 is converted to a digital signal by an analog-to-digital converter (AD converter) and then outputted from an output bus N such that the information unit (not shown) can perform corresponding activities according to the outputted digital signal.
FIG. 1 shows a conventional switching module having a switching circuit 90 connected to an AD converter 80 in series, and an input voltage of the AD converter 80 is Vin1. The switching circuit 90 includes four switches SW4, SW3, SW2 and SW1, and the conducting states of these switches are determined by a jack state or a key state of a jack or key device or its signal. In addition, the conducting priority of the switches SW4, SW3, SW2 and SW1 of the switching circuit 90 is SW4>SW3>SW2>SW1. When the switch SW4 is turned on (conduction), then Vin1=0 volt; when the switch SW3 is turned on, then Vin1=VCC×/(R5+R4) volt; when the switch SW2 is turned on, then Vin1=VCC×(R4+R3)/(R5+R4+R3) volt; when the switch SW1 is turned on, then Vin1=VCC×(R4+R3+R2)/(R5+R4+R3+R2) volt; and when all the switches are OFF, then Vin1=VCC×(R4+R3+R2+R1)/(R5+R4+R3+R2+R1) volt. Generally, the input voltage Vin1 is non-linearly varied in accordance with different conducting states; therefore, the interval of comparison voltage of the AD converter 80 has to be non-linear, or a higher bit rate AD converter has to be utilized.
FIG. 2 shows another conventional switching circuit 91 cascaded with an AD converter 80. In this case, the switches SW4, SW3, SW2 and SW1 of the switching circuit 91 have identical conducting priorities, i.e. their ON and OFF states are determined by the jack or key state or the signal from the jack or key device. Normally, under different conducting states of the switches, an input voltage Vin2 of the AD converter 80 various non-linearly. In this manner, the interval of comparison voltage of the AD converter 80 has to be non-linear, or a higher bit rate AD converter has to be utilized. However, this will increase the complexity of signal recognition.